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 Features
* * * * * * * * *
1024 x 1024 Pixels with Memory Zone Up to 60 Images/Second Built-in Antiblooming Device Providing an Electronic Shutter Function Pixel: 14 m x 14 m Image Zone: 14.34 x 14.34 mm Four Outputs (256 x 1024 pixels) at 20 MHz Each Possible Binning 2 x 2 Optical Shield against Parasitic Reflexions and Stray Light A/R Window in 400 - 700 nm Bandwidth
Description
The TH7887A is especially designed for high data rate applications (up to 60 pict/s) in medical and industrial fields. This area array image sensor consists of a 1024 x 1024 pixels (14 m x 14 m) image zone associated to a memory zone (masked with optical shield). In order to increase data rate, the image zone is divided into four zones (256 x 1024 each) which are read in parallel through 4 different outputs (readout frequency up to 20 MHz/output leading to a total readout frequency of 80 MHz). The TH7887A is designed with antiblooming gates. Moreover, the 2 x 2 binning mode is available on this sensor. In this case, the image size is 512 x 512 with 28 m x 28 m pixels. Each output will read 128 x 512 pixels. The TH7887A is sealed with a specific anti-reflective window optimized in 400 700 nm bandwidth.
Area Array CCD Image Sensor 1024 x 1024 Pixels with Antiblooming TH7887A
Rev. 2146A-IMAGE-05/02
1
Figure 1. TH7887A Organization
P M
1, 2, 3, 4 1, 2, 3, 4
A
VA
1024 x 1024 Image Zone
1024 x 1024 Memory Zone
M
L 1,2
VGS
R
VDD1 VS1 VDD2 VS2 VDD3 VS3 VDD4 VS4 VOS1 VOS2 VOS3 VOS4
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Pin Identification
R L1 AA
VSS VDDP N.C VSS VDR VS4 VOS4 VOS3 VOS2 VOS1
W
VS3 VS2 VS1 VSS
L2 M
V
VGS VDD4 VDD3 VDD2 VDD1 VSS
A
VSS VSS
M4 M3 P3 M2 P2 P1 M2
VSS
C
VA
P2 M3
VSS
P3
B
VSS
M1 P4 P1 M4 M1 P4 7 6 5 4 3 2
A
VSS
8
1
TOP VIEW
Pin Number A2, A6
(1) (1) (1)
A1 Index
Symbol P4 P3 P2 P1 M1 M2 M3 M4 M L1 L2 VDD1 VDD2
Designation
B2, C5 B5, C3
Image zone clocks
A5, C2(1) A3, A7
(1) (1) (1)
B7, C4 B4, C6
Memory zone clocks
C7, A4(1) V7 W8 V8 V2 V3 V4 V5 W2 W3 W4 W5 AA6 AA5 V6
Memory to register clock Readout register clocks
Output amplifier drain supply VDD3 VDD4 VS1 VS2 Output amplifier source supply VS3 VS4 VDDP NC VGS Screen voltage Not connected Register output gate bias
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Pin Number AA1 AA2 AA3 AA4 AA8 C8 W6 C1 AA7, V1, W1 W7, A8, B8
Symbol VOS1 VOS2
Designation
Video output signal VOS3 VOS4 R A VDR VA VSS VSS Substrate bias Reset clock Antiblooming gate clock Reset bias Antiblooming diode bias
B6, B1, A1, B3 VSS Note: 1. Short circuited on package.
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Geometrical Characteristics
The image zone features 1024 useful lines (+ 20 extra lines) of 1024 pixels. For readout only, the full frame is split into 4 blocks of 256 columns. The video line consists of 256 useful pixels, and 273 elements in total (for each output).
Figure 2. Video Line (on each output)
7 dark reference lines
3 isolation lines
Image zone
1024 useful pixels
1044 line
First pixel 6 dark reference lines
3 isolation lines 1 inactive line
Memory zone
1044 line
Vos1
Vos2
Vos3
Vos4
Pixels 1 to 17 : inactive prescan elements Pixels 18 to 273 : useful elements
5
2146A-IMAGE-05/02
Figure 3. Pixel Layout
A
VA
A
A
A
VA
A
P1 P2
14 m
P3 P4 P1
A'
Aperture 10.3 m 14 m
Figure 4. Cross-section AA'
P1 P2 P3 P4 P1
14 m Transfer direction
Potential profile during integration time
Signal charge for one pixel
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Absolute Maximum Ratings*
Storage Temperature .................................... -55C to + 150C Operating Temperature............................... -40C to + 85C *NOTICE: Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Thermal Cycling.........................................................15C/mm Maximum Applied Voltages: A2, A6, B2, C5, B5, C3, A5, C2, A3, A7, B7, C4 B4, C6, C7, A4, V7, W8, V8, AA8, V6, AA5.......... -0.3V to 15V V2, V3, V4, V5, W2, W3, W4, W5 W6, C1, AA6 ......................................................-0.3V to 15.5V C8 ......................................................................... -0.3V to 12V AA7, V1, W1, W7, A8, B8, B6, B1, A1, B3 ............. Ground 0V
Operating Range
The operating range defines the limits where function is guaranteed. Electrical limits of applied signals are given in the operating conditions section.
Operating Precautions Operating Conditions
Table 1. DC Characteristics
Shorting the video outputs to any other pin, even temporarily, can permanently damage the on-chip output amplifier.
Value Parameter Output amplifier drain supply Screen voltage Reset bias Antiblooming diode bias Register output gate bias Output amplifier source supply Ground Symbol VDD1, VDD2, VDD3, VDD4 VDDP VDR VA VGS VS1,2,3,4 VSS Min 14.5 14.5 14.5 14.5 2.2 - - Typ 15 15 15 15 2.5 0 0 Max 15.5 15.5 15.5 15.5 2.8 - - Unit V V V V V V V
7
2146A-IMAGE-05/02
Timing Diagram
The following diagrams are given for: * * * * 20 MHz readout frequency 1.25 MHz vertical transfer frequency image zone to memory zone transfer memory zone to register transfer and readout of register
Readout of one image is performed in 2 steps:
This last step is also an integration period, the duration of which can also be increased according to the required frame rates. Figure 5. Frame Timing Diagram
Image to memory zone Integration period
Transfer
A
Picture readout Memory zone
P1 P2 P3 P4
1 5 1044
Cleaning period (*)
1044 pulses
M1= M
M2 M3 M4
See fig. 7 1 5 1044
L1 L2 R
See fig. 6
(*) During the cleaning period, memory clocks must be pulsed as during readout time (specially for high temperature applications).
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TH7887A
Figure 6. Line Timing Diagram
Item fig.8 7To
M1= M M2 M3 M4
See fig. 9
5To
5To 3To
3To 3To 100 ns min.
3To 100 ns min.
L1 L2 R
Vos 1,2,3,4
1 17 18 273 min 1 17
1
2
1
1 : 17 inactive pre-scan elements 2 : 256 useful video pixels
Figure 7. Vertical Transfer During Image to Memory Zone Transfer
20 ns < tf < 2 To
100 ns min. 100 ns min.
20 ns < tr < 2 To
A
1 2 1044
P1 P2 P3 P4
M1= M M2 M3 M4
See fig. 8
9
2146A-IMAGE-05/02
Figure 8. Transfer Period from Image Zone to Memory Zone (P and M) for 1.25 MHz Vertical Transfer Frequency (Fv = 1/Tv)
Tv=800 ns P1 = M1
tr 5 To tf 3 To
25 ns < tr < To/3 25 ns < tf < To/3
5 To
P2 = M2 To = 100 ns P3 = M3
3 To 5 To
P4 = M4
To = Tv / 8 3 To
Figure 9. Output Diagram for Readout Register and Reset Clock 20 MHz Applications
50 ns
16 ns min
16 ns min
L1
t1 t1
L2
A 12 ns min 0.3A
R
t2 td t2 td
Vos 1,2,3,4
Signal level Reset feedthrough t1 = 10 ns typ. t2 = 5 ns typ. td = 8 ns typical delay time
Cross over of complementary clocks ( L1, L2) between 30% and 70% of maximum amplitude.
10
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Binning Mode Operation
In this mode, the image is composed of 512 x 512 pixels (28 m x 28 m each).
Figure 10. Summation in the Readout Register of 2 Adjacent Lines.
15 To
Fall times and rise times: see figures 8 & 9
5To 3To 5To
M1
5To 3To 5To
M2 M3 M1
3To 5To 3To 3To
3To
3T0
5To
3To
M = M1
100 ns min 100 ns min
L1 L2
Figure 11. Summation of 2 Adjacent Pixels
L1
L2
Output reset frequency divided by 2
R
Vos 1,2,3,4
Pixel i Useful signal Pixel i + Pixel i+1
In binning mode operation maximum level of elementary pixel (14 x 14 m) is reduced to Vsat/4.
11
2146A-IMAGE-05/02
Exposure Time Reduction
The TH7887A allows exposure time control (electronic shutter function). The exposure time reduction is achieved by pulsing all the Pi gates to 0V to continuously remove all photogenerated electrons through antiblooming drain VA. Figure 12. Timing Diagram for Electronic Shutter
Image period
A
1 s 1 s
P1
P2
P3
P4
Transfer
Obturation
Integration
Fall times and rise times: see figures 7 & 8
Table 2. Drive Clock Characteristics
Value Parameter Image zone clocks High level Low level Memory zone clocks High level Low level Memory to register clocks High level Low level Antiblooming gate High level (integration) Low level (transfer) M 8.5 0 A 5.5 0 5.5 0.5 5.5 0.8 V V 9 0.5 9.5 0.8 V V M1, 2, 3, 4 8.5 0 9 0.5 9.5 0.8 V V Symbol P1, 2, 3, 4 8.5 0 9 0.5 9.5 0.8 V V Min Typ Max Unit Remarks Typical input capacitance 15 nF See Figure 13 Typical input capacitance 15.5 nF See Figure 13 Typical input capacitance 10 nF Typical input capacitance 14 nF See Figure 13 and Figure 15
12
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TH7887A
Table 2. Drive Clock Characteristics (Continued)
Value Parameter Reset gate High level Low level Readout register clocks High level Low level L1, 2 8.5 0 9 0.5 9.5 0.8 V V Symbol R 10 0 11 0.5 12 0.8 V V Min Typ Max Unit Remarks Typical input capacitance 10 pF
L1
50 pF
L2
60 pF
75 pF
Maximum readout register frequency Image zone to memory zone transfer frequency
FH FV
- -
20 1.25
23 1.7
MHz MHz
See Figure 9 See Figure 14
Figure 13. Capacitance Network for Drive Clocks
P2
3.4 nF 2.5 nF
P2
0.7 nF 2.5 nF 0.5 nF 0.5 nF
P1
3.3 nF
A
P3
1.4 nF
P1
0.7 nF
VA
P3
1.3 nF
P4
P4
A
3.2 nF
P1
4.4 nF
4.9 nF
P2
4.4 nF
2.2 nF
2.2 nF
4.4 nF
3.4 nF
P4
P3
3.9 nF
M1
4.4 nF
4.4 nF
M2
4.4 nF
3.2 nF
3.2 nF
4.4 nF
3.9 nF
M4
M3
13
2146A-IMAGE-05/02
Electrical Performances
Table 3. Static and Dynamic Electrical Characteritics
Value Parameter Output amplier supply current Output impedance DC output level Output conversion factor Symbol IDD ZS VREF CVF Min - 200 - 7.8 Typ 8.5 225 11.5 8 Max - 250 - 8.2 Unit mA V V/ eRemarks per amplifier
Electro-optical Performances
*
General test conditions: - - - - Top = 25C (package back temperature). Light source: 2854K with 2 mm BG38 filter (unless specified) + F/3.5 optical aperture. 60 images per second mode (unless specified). Typical operating conditions.
* *
Readout on each output. Measurements exclude dummy elements and blemishes.
Table 4. Electro-Optical Performance Characteristics
Value Parameter Saturation output level Responsivity at 640 nm Responsivity with BG38 filter Quantum efficiency at 640 nm Gain dispersion between outputs Photo response non-uniformity (1) Dark signal non-uniformity (1) Average dark signal Temporal RMS noise in darkness (Last line) Dynamic range Symbol VSAT R QE G PRNU DSNU VDS VN D Min 1.6 7 - - - - - - - - - Typ 2 8 12 14 1 1.3 0.14 1 2 200 80 Max 2.4 - - - 2 1.7 0.2 1.5 2.8 - - Unit V V/J/cm2 mV/lux % % % VOS mV mV mV V dB
(2) (3) (4)
Remarks
(1)
See Figure 17
(5)
(6)
14
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2146A-IMAGE-05/02
TH7887A
Table 4. Electro-Optical Performance Characteristics (Continued)
Value Parameter Horizontal modulation transfer function at 500 nm Vertical charge transfer inefficiency Horizontal charge transfer inefficiency Notes: Symbol MTF VCTI HCTI Min - - - Typ 70 - - Max - 2.10-5 7.10-5 Unit % Remarks
(7)
(8)
(9)
1. Pixel saturation (full well) as a function of vertical transfer frequency (see Figure 14) and antiblooming adjustment (see Figure 15). 2. After subtraction of dark signal slope due to memory readout time. 3. First line level referenced from inactive prescan elements (17 samples). 4. Last line level referenced from inactive prescan elements(17 samples). 5. Measured with Correlated Double Sampling (CDS) including 160 V readout noise and dark current noise in the general test conditions. 6. Saturation to RMS noise in darkness ratio. 7. At Nyquist frequency. 8. VSAT/2 measurement and 1.25 MHz vertical transfer frequency. 9. VSAT/2 measurement and 20 MHz horizontal transfer frequency.
Figure 14. Saturation Level by full well with antiblooming out (A high = 0V) vs the Vertical Transfer Frequency
3.5
3 Readout stage limit Saturation Output Level (Volts) 2.5
2
1.5
1
0.5
0 200
700
1200
1700
Vertical Transfer Frequency (KHz)
15
2146A-IMAGE-05/02
Figure 15. Saturation Level Limitation by the Antiblooming Effect on the Pixel
3 Readout stage limit Saturation Output Level (Volts) 2.5 Inefficient antiblooming Efficient antiblooming
2
1.5
1
0.5 1.2 MHz vertical transfer frequency 0 2 3 4 5 6 7 8 9 A High Clock Level (Volts)
Figure 16. Smearing Effect
100 60 images / sec. 1.2 MHZ vertical tranfer frequency 80 Smearing/Vsat (%) Vertical smearing Overillumination 100xEsat 40 a b
60
20 Smearing level 10xEsat 0 0 1 2 3 4 5 6 7 8 9 10 Overilluminated Zone (% Image Height) a,b signal line
16
TH7887A
2146A-IMAGE-05/02
TH7887A
Figure 17. Spectral Response
20
Quantum efficiency (%)
15
10
5
0 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 Lambda (mm)
Image Quality Grade
Blemish Clusters Columns General Measurement Conditions
Max area of 2 x 2 defective pixels. Less than 7 contiguous defects in a column. More than 7 contiguous defects in a column.
Room temperature Frequency Considered image zone Light source
25C 60 images/second typical operating conditions 1024 x 1024 2854 K with BG38 filter + F/3.5 optical aperture
Table 5. At VOS = 0.7 Vsat.
Type Blemishes/clusters Columns White > 10% Vos
i i e
Black > 30% Vos > 10% Vos
> 20% VosS
Table 6. In darkness, T = 25C, 60 images/second
Blemishes/clusters Columns Note: 1. Reference is Vo : average darkness signal > 10 mV(1) > 5 mV(1)
2146A-IMAGE-05/02
e
17
Number of Defects
Total pixel number affected by blemishes and clusters Maximum number of clusters Maximum number of columns 100 10 5
: amplitude of video signal of defect with respect to mean output voltage Vos
Ordering Code
TH7887AVRH
18
TH7887A
2146A-IMAGE-05/02
TH7887A
Outline Drawing
TOP VIEW
55.88 42.5
33.5
28.5
x
y
2.540.25
x = 0.45 0.10 y = 7.17 0.10
1.75
0.51
3.640.40
1.060.1
36.6
0.46
2.54
14.25
2.54 typ
2.2 0.04
4.6
25
1st useful pixel - readout through Vos1 Photosensitive area Glass window thickness: 1.5 0.1 mm (antireflective coating with 400 - 700 nm transmission: 99%) A1 index Optical shield
12345678
40.64
C B A
2.2 0.05
BOTTOM VIEW
All values in mm Tolerance unless specified 1%
Reference for first pixel position Optical distance between photosensitive area and - external face of the window: 1.93 0.30 mm - back side of the package: 1.71 0.15 mm Metal plate connected to VSS Parallelism between CCD and back side has a maximum value of 100 m
32.25
AA W V
19
2146A-IMAGE-05/02
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
2146A-IMAGE-05/02 0M


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